SMJ34020A_06 Datasheet, PDF (41/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
As a special 1-megabit VRAM control cycle, the clock strech is also performed when the PMASKL and PMASKH
registers are set to nonzero values, CST in DPYCTL is cleared, VEN in CONFIG is set, and the byte-aligned
pixel-write instruction is executed (Figure 20). This cycle is indicated by CAS, TR/ QE, and SF high and WE low
at the falling edge of RAS and by SF low at the falling edge of CAS. The data on LAD is written to memory just
as a normal DRAM write except that data in the write mask is used to enable DQs that are written to memory.
During the address portion of the cycle, the status on LAD0 −LAD3 indicates that a pixel operation is being
performed (status code = 1101).
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
Data Out 1
Data Out 2
CAMD
RCA
Row
1st Column
2nd Column
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 20. Write-Cycle Timing Using Mask
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