SMJ34020A_06 Datasheet, PDF (37/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Clock stretch is a special 1-megabit VRAM control cycle that is executed when VEN in the CONFIG I/O register
is set and PMASKL and/or PMASKH are written (Figure 16). This cycle is indicated by CAS, WE, TR/ QE, and
SF high at the falling edge of RAS and SF low at the falling edge of CAS. As the plane mask is copied to the
PMASK register(s), it is also output on LAD to be written to a special register on the VRAM that is used in
subsequent cycles requiring a write mask. During the address portion of the cycle, the status on LAD0−LAD3
indicates a write-mask load is being performed (status code = 0110). Although CAMD, PGMD, and SIZE16 are
ignored on this cycle, they should be held at valid levels as shown.
Write to the PMASK I/O Register
Load-Write-Mask Cycle
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
GI
LAD
PMASK Address
PMASK Data
Zero Address
Not PMASK Data
CAMD
RCA
PMASK Row
PMASK Column
All-Zero Address
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 16. Load-Write-Mask-Cycle Timing
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