SMJ34020A_06 Datasheet, PDF (47/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
In Figure 25, transition points are shown for R0 and R1 to indicate where they occur relative to the other signals.
This example indicates that the SMJ34020A has control of the bus, yields control, and then regains control. The
SMJ34020A regains bus mastership as soon as GI is driven active (low). R0 and R1 could be outputting any
of the codes with the exception of the access-termination code. The bus arbitration logic must control the timing
of GI to all of the processors requiring the bus.
It is recommended that SMJ34020A clock stretch not be used in multiprocessor systems.
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