SMJ34020A_06 Datasheet, PDF (43/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Address
Subcycle
Wait
State
Cycle
Completion
Q4 Q1 Q2 Q3 ^Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
CAMD
RCA
Row
Tap Point
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 21. Memory-to-Serial-Data-Register-Cycle Timing (VRAM Read Transfer)
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
43