SMJ34020A_06 Datasheet, PDF (31/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
The refresh pseudo-address output to RCA0 −RCA12 and LAD0 −LAD31 comes from the 16-bit refresh
address register (I/O register C000 01F0h) that is incremented after each refresh cycle (Figure 13). The 16 bits
of address are placed on LAD16 −LAD31; all other LAD bus lines are zero. The logical addresses on
RCA0−RCA12 corresponding to LAD16 −LAD31 also output the address from the refresh-address register.
Although PGMD and SIZE16 are ignored during a refresh cycle, they should be held at valid levels. LRDY and
BUSFLT are not sampled until the start of the first Q2 cycle after RAS has gone low.
If a refresh cycle is aborted due to a high-priority bus request (assuming LRDY is low at Q2 after RAS low), a
bus fault, or an external retry, then the count of refreshes pending is not decremented and the same
pseudo-address is reissued when the refresh is restarted.
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