SMJ34020A_06 Datasheet, PDF (90/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
video-shift-clock timing: SCLK (see Figure 53)
NO.
117 tc(SCK)
Cycle time, period of video serial clock SCLK
118 tw(SCKH)
Pulse duration, SCLK high
119 tw(SCKL)
Pulse duration, SCLK low
120 tt(SCK)
Transition time, (rise and fall) of SCLK
* This parameter is not production tested.
’34020A-32
MIN MAX
35
50
12
12
2*
5*
’34020A-40
MIN MAX
25
50
10
10
2*
5*
UNIT
ns
ns
ns
ns
SCLK
117
118
119
120
120
Figure 53. Video-Shift-Clock Timing: SCLK
video-interface timing: VCLK and video outputs (see Figure 54)
NO.
123 tc(VCK)
Cycle time, period of video input clock VCLK
124 tw(VCKH)
Pulse duration, VCLK high
125 tw(VCKL)
Pulse duration, VCLK low
126 tt(VCK)
Transition time, (rise and fall) of VCLK
127
td(VCKL-HSL)
Delay time, VCLK low to HSYNC, VSYNC, CSYNC / VBLNK or
CBLNK / VBLNK low
Delay time, VCLK low to HSYNC, VSYNC, CSYNC / HBLNK, or
128 td(VCKL-HSH) _{CBLNK / VBLNK high}
129
th(VCKL-HSL)
Hold time, VCLK no longer high to HSYNC, VSYNC,
CSYNC / HBLNK, or CBLNK / VBLNK no longer high
130
th(VCKL-HSH)
Hold time, VCLK no longer high to HSYNC, VSYNC,
CSYNC / HBLNK, or CBLNK / VBLNK no longer low
* This parameter is not production tested.
’34020A-32
MIN MAX
62.5 100
28
28
2*
5*
40
40
0*
0*
’34020A-40
MIN MAX
62.5 100
28
28
2*
5*
40
40
0*
0*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
VCLK
123
124
125
126
126
HSYNC
VSYNC
CSYNC / HBLNK
CBLNK / VBLNK
(outputs)
127
129
128
130
Figure 54. Video-Interface Timing: VCLK and Video Outputs
90
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