SMJ34020A_06 Datasheet, PDF (56/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
In Figure 30, SMJ34020A provides HRDY as soon as it recognizes the host write cycle (if no other host write
cycle is in progress), allowing the host to latch the data in the external data latches. The host then attempts a
second write but does not get an immediate HRDY because the SMJ34020A is still writing the first data to
memory. As soon as the memory write completes, HRDY goes high so that the host can latch the new data. The
SMJ34020A then writes the second data while the host continues other processing. The host access request
is synchronized to the SMJ34020A at the beginning of Q4 so that the local memory cycle can begin in Q1. If
the external host access request occurs after the setup time requirement before Q4, the request is not
considered until the next Q4 cycle. During a host write cycle DDIN is active so that if the write is to the
SMJ34020A I/O registers, the data can be required within the GSP.
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