SMJ34020A_06 Datasheet, PDF (70/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
CLKIN and RESET timing requirements (see Figure 40)
SMJ34020A-32
34020A-40
NO.
UNIT
MIN
MAX
MIN
MAX
1 tc(CKI)
Cycle time, period of CLKIN (4tQ)
31.25
2 tw(CKIH)
Pulse duration, CLKIN high
10
3 tw(CKIL)
Pulse duration, CLKIN low
10
4 tt(CKI)
Transition time, CLKIN
2*
5 th(CKI-RSL) Hold time, RESET low after CLKIN high
15†
Setup time, RESET high to CLKIN no longer
6 tsu(RSH-CKI) _low
10†
7 tw(RSL)
Pulse duration, ^{Initial reset during powerup}
RESET low
Reset during active operation
160tQ − 40‡
16tQ − 40‡
8
tsu(CSL-RSH)
Setup time, HCS low to RESET high to
configure self-bootstrap mode
8tQ + 55
50
25
8
8
5*
2†
12‡
6‡
160tQ − 40‡
16tQ − 40‡
8tQ + 55
50 ns
ns
ns
5* ns
ns
ns
ns
ns
9
td(CSH-RSH)
Delay time, HCS no longer low to RESET high
to configure self-bootstrap mode
4tQ − 50§
4tQ − 50§
ns
10 tw(CSL)
Pulse duration, HCS low to configure GSP in
self-bootstrap mode
4tQ + 55
4tQ + 55
ns
† _{These timings are required only to synchronize the SMJ34020A to a particular quarter cycle.}
‡ _{The initial reset pulse on powerup must remain valid until all internal states have been initialized. Resets applied after the SMJ34020A has been}
initialized need to be present only long enough to be recognized by the internal logic; the internal logic maintains an internal reset until all internal
states have been initialized (34 LCLK1 cycles).
§ _{Parameter 9 is the maximum amount by which the RESET low-to-high transition can be delayed after the start of the HCS low-to-high transition}
and still assure that the SMJ34020A is configured to run in the self-bootstrap mode (HLT bit = 0) following the end of reset.
* The parameter is not production tested.
1
3
4
2
4
CLKIN
RESET
6
5
HCS
7
8
9
10
Figure 40. CLKIN and RESET Timing Requirements
70
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