SMJ34020A_06 Datasheet, PDF (54/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
The host read of the SMJ34020A I/O registers (Figure 29) suppresses the generation of TR / QE and CAS so
that data is read from the SMJ34020A rather than from memory. DDOUT is enabled so that data can flow
through external buffers on LAD to the host data latches. The SMJ34020A I/O registers can be accessed in any
of the host access modes (random/same, block, or read-modify-write).
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