SMJ34020A_06 Datasheet, PDF (34/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Q4 Q1 Q2 Q3 Q4^† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK1
LCLCK2
GI
LAD0 −LAD15
Low Address
Low
Hi
LAD16 −LAD31
High Address
CAMD
RCA
(see Note A)
ALTCH
Row
Column (S=0)
Column (S=1)
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
NOTE A: RCA0 can be used to determine accesses to odd or even words because it outputs the least significant bit
of the word address during the column-address time (except in 4-M mode with CAMD = 1).
Figure 14. Dynamic Bus Sizing, Read Cycle Timing
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