SMJ34020A_06 Datasheet, PDF (87/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
multiprocessor-interface timing: GI, ALTCH, RAS, R0 and R1 (see Figure 51)
’34020A-32
’34020A-40
NO.
MIN
MAX
MIN
MAX
105 ta(GIV-RQV)
Access time, GI valid after R0 and R1 valid
(see Note 12)
2tQ −40
2tQ −30
105.1 tsu(GIV-CK1H)
Setup time, GI valid before LCLK1 no longer low
(see Note 12)
40
35
106 th(CK1H-GIV)
Hold time, GI valid after LCLK1 no longer low
0
107 td(CK2H-RQV) Delay time, LCLK2 no longer low to R0 or R1 valid
108 td(CK2H-RQNV) Delay time, LCLK2 high to R0 or R1 no longer valid
tQ −15
NOTE 12: These timings must be met to ensure that GI is recognized on this clock cycle.
0
tQ + 15
tQ −13.5
tQ + 13.5
UNIT
ns
ns
ns
ns
ns
For a SMJ34020A to gain control of the local bus during a given cycle, GI must be low at the start of Q1 (indicating
that the bus arbitration logic is granting the bus to this processor).
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLK1
LCLK2
105.1
107
108
R0 −R1
GI
106
105
Valid
Valid
† _{See clock stretch, page 21.}
† _{See clock stretch, page 21.}
Figure 51. Multiprocessor-Interface Timing: GI, ALTCH, RAS, R0 and R1
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