SMJ34020A_06 Datasheet, PDF (14/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
reset
Reset puts the SMJ34020A into a known initial state. This state is entered when the input signal at RESET is
asserted low. While RESET remains asserted, all outputs are in a known state, no DRAM refresh cycles take
place, and no screen refresh cycles are performed.
The state of the HCS input on the CLKIN cycle before the low-to-high transition of RESET determines whether
the SMJ34020A is halted or begins executing instructions. The SMJ34020A can be in one of two modes,
host-present or self-bootstrap mode.
Host-present mode: if HCS is high at the end of reset, SMJ34020A instruction execution halts and remains
halted until the host clears the HLT (halt) bit in HSTCTLH (host control register). Following reset, the RAS cycles
required to initialize the dynamic RAMs are performed automatically by the GSP memory control logic. The host
can request a memory access after the eight RAS initialization cycles have completed. The SMJ34020A
automatically performs DRAM refresh cycles at regular intervals although the SMJ34020A remains halted until
the host clears the HLT bit. Only then does SMJ34020A fetch the level-0 vector address from location
FFFF FFE0h and begin executing the reset service routine.
Self-bootstrap mode: if HCS is low at the end of reset, the SMJ34020A first performs eight refresh cycles to
initialize the DRAMs. Immediately following the eight refresh cycles, the GSP fetches the level-0 vector address
from location FFFF FFE0h and begins executing the reset service routine.
At the time the SMJ34020A fetches the level-0 vector address (the reset vector), the least significant four bits
(bit address part) are used to load configuration data that establishes the initial condition of the
big-endian/little-endian mode and the current RCA bus configuration bits in the CONFIG register as described
in the I/O register section.
Unlike other interrupts and software traps, reset does not save the previous ST or PC values (this can also occur
on host initiated nonmaskable interrupts if the NMIM bit in HSTCTLH is set to a 1) because the value of the stack
pointer just before a reset is generally not valid. Saving these values on the stack could contaminate valid
memory locations. A TRAP 0 instruction, which uses the same vector address as reset, similarly does not save
the ST or PC values.
asserting reset
A reset is initiated by asserting RESET to its active-low level. To reset the SMJ34020A at powerup, RESET must
remain active low for a minimum of 40 local clock periods (LCLK1 and LCLK2) after power levels have become
stable. At times other than powerup, the SMJ34020A can be reset by holding RESET low for a minimum of four
local clock periods; the GSP enters an internal reset state for 34 local clock cycles. While in the internal reset
state and RESET is high, memory-refresh cycles occur.
reset and multiprocessor synchronization
The synchronization of multiple SMJ34020As sharing a local memory is done using the RESET input. In
systems where the multiprocessor interface is used to control the access to a common memory, the processors
must be synchronized. Synchronization is achieved by taking RESET high within a specific interval relative to
CLKIN. This can be done by using CLKIN to clock the RESET as received by the SMJ34020As. All SMJ34020As
to be synchronized should use the same CLKIN and RESET inputs. All of the local memory and bus control
signals should be connected in parallel (without buffers) between the processors. After powerup, the
processors are not necessarily synchronized with respect to the particular quarter cycle in progress. The rising
edge of RESET is used to set the SMJ34020A to a particular quarter cycle by adding Q1 cycles. All SMJ34020As
in a multiprocessor environment operate on the same quarter cycle within 10 quarter cycles after the rising edge
of RESET.
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