SMJ34020A_06 Datasheet, PDF (69/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
general notes on timing parameters
The period of the local clocks (LCLK1 and LCLK2) is four times the period of the input clock (CLKIN).
The quarter cycle time (t_Q) that appears in the following tables is one quarter of a local output clock period or
equal to the input clock period, t_c(CKI).
All output signals from the SMJ34020A are derived from an internal clock such that all output transitions for a
given quarter cycle occur with a minimum of skewing relative to each other. In the timing diagrams, the
transitions of all output signals are shown with respect to the local clocks (LCLK1 and LCLK2). The local clock
edge used as a reference occurs one internal clock cycle before the transition specified.
The signal combinations shown in the timing parameters are for timing reference only; they do not necessarily
represent actual cycles. For actual cycle descriptions, see the cycle timing section of this specification.
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