SMJ34020A_06 Datasheet, PDF (33/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
When SIZE16 is selected low (Figure 14), the SMJ34020A performs a second cycle to read (or write) the
remaining 16 bits of the word. Reads always access all 32 bits (all CAS strobes are active). Internally, the
SMJ34020A latches both the high and the low words obtained on the first read cycle. The sense of SIZE16 on
the second (odd-word) access is used to determine which half of the bus is to be sampled to replace the data
word latched during the first cycle.
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