SMJ34020A_06 Datasheet, PDF (44/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
This VRAM cycle shown in Figure 22 is performed when a video timeout occurs due to a match of the MLRNXT
register, VCE in DPYCTL is cleared, and SSV in DPYCTL is set. This cycle is indicated by TR/ QE low and CAS,
SF, and WE high at the time RAS goes low. The timing of the low-to-high transition of TR/ QE is not dependent
upon the timing of SCLK because there is not as great a timing constraint to position the cycle as in midline
reload. During the address portion of the cycle, the status on LAD0 −LAD3 indicates a video-initiated VRAM
memory-to-register transfer (status code = 0100). Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
CAMD
RCA
Row
Tap Point
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 22. Memory-to-Split-Serial-Data-Register-Cycle Timing (VRAM Split-Register Read Transfer)
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