SMJ34020A_06 Datasheet, PDF (26/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
LCLK1
LCLK2
GI
LAD (SMJ34020A)
(see Note A)
LAD (Memory)
(see Note A)
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/ QE
SF
DDIN
DDOUT
LRDY
(see Note B)
PGMD
(see Note B)
SIZE16
(see Note B)
BUSFLT
(see Note B)
R0
Standard Memory Read Cycle
Page-Mode Read
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Address
Row
Data
1st Column
Data
2nd Column
R1
† _{See clock stretch, page 21.}
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (memory): Output to LAD by the memory.
B. LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle accesses to
32-bit-wide memory space.
Figure 9. Local-Memory Read-Cycle Timing (With Page Mode)
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