SMJ34020A_06 Datasheet, PDF (49/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Two SMJ34020As use the multiprocessor interface to pass control of local memory from one to the other
(Figure 26). GSP1 completes a read cycle to the local memory and, although desiring another read, loses the
bus to GSP2, which does a single write cycle (perhaps a host-write access). GSP1 then regains control and
completes the read cycle (shown with a single wait state). Since no further memory-access requests are
present, GSP1 maintains control of the bus and holds all of the local-memory control signals at their inactive
levels. LRDY is a common input to both GSP1 and GSP2.
The host cycle timing diagrams shown in this data sheet are only a sample. For more information, see the
TMS34020 User’s Guide.
GSP1 Read
GSP2 Write
GSP1 Read With Wait
Bus Idle
1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1
GI
R0
R1
RAS
CAS
WE
TR / QE
GSP1
DDIN
DDOUT
ALTCH
LRDY
ALTCH
1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1 2 34 1
GI
R0
R1
RAS
CAS
GSP2
WE
TR / QE
DDIN
DDOUT
Figure 26. Multiprocessor-Interface Cycle Timing (Passing Control)
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