SMJ34020A_06 Datasheet, PDF (79/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
local-bus timing: bus control inputs (see Note 5 and Figure 47)
NO.
52
ta(CMV-LAV)†
53
th(LA-CMV)†
Access time, CAMD valid after address valid on LAD
Hold time, CAMD valid after address no longer valid
on LAD
34020A-32
MIN
MAX
3tQ −45
0
34020A-40
MIN
MAX
3tQ −37
UNIT
ns
0
ns
54
ta(BCV-ALL)†
Access time, control valid (LRDY, PGMD, SIZE16,
BUSFLT) after ALTCH low
3tQ −35 + s
3tQ −27 + s ns
55
th(CK2H-BCV)†
Hold time, control (LRDY, PGMD, SIZE16, BUSFLT)
valid after LCLK2 high
0
0
ns
56
tsu(BCV-CK2H)†
Setup time, SIZE16 valid before LCLK2 no longer
low
20
15
ns
† _{CAMD, LRDY, PGMD, SIZE16, and BUSFLT are synchronous inputs. The specified setup, access and hold times must be met for proper device}
operation.
NOTE 5: s = tQ if using the clock stretch;
s = 0 otherwise
LCLK1
LCLK2
LAD
CAMD
ALTCH
LRDY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4‡ Q1 Q2 Q3 Q4 Q1
Address
52
53
Valid
55
54
Valid
PGMD
SIZE16
Valid
Valid
56
55
Valid
BUSFLT
‡ _{See clock stretch, page 21.}
Valid
Figure 47. Local-Bus Timing: Bus Control Inputs
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