SMJ34020A_06 Datasheet, PDF (39/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
The clock stretch is also performed when a VBLT or VFILL instruction is executed and PMASKL and PMASKH
are set to zero (Figure 18). It is indicated by CAS, WE, TR/ QE high and SF low at the falling edge of RAS and
by SF high at the falling edge of CAS. The data on LAD is used as an address mask, and the data stored in the
color latch is written to the VRAM. The address selects chosen by the two least significant bits of the column
addresses within the VRAM are replaced with the four DQ bits latched on the falling edge of CAS. A logic 1 on
each bit enables that nibble to be written, while a logic 0 disables the write from occurring. This cycle allows up
to 16 bits to be written into each VRAM (four adjacent nibbles, each set to the value in the color latch) for a total
of 128 bits. During the address portion of the cycle, the status on LAD0−LAD3 indicates a block write is being
performed (status code = 1110). SIZE16 can be used with this cycle, but external multiplex logic is required to
map the data correctly to appropriate memories.
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
Data Out 1
Data Out 2
CAMD
RCA
Row
1st Column
2nd Column
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 18. Block-Write-Cycle Timing (Without Mask)
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