SMJ34020A_06 Datasheet, PDF (23/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
enabling clock stretch (continued)
When stretch mode is enabled, the following machine cycles are stretched:
D All address cycles of all memory-access sequences
D Read data cycles in read-modify-write sequences
Notes:
a) The host default cycle shown in the TMS34020 User’s Guide is not stretched because it is not a true
address cycle; that is, RAS, etc., do not go low.
b) The CPU default cycle, which is similar to the host default cycle in that RAS, etc., do not go low, is
also not stretched.
c) Clock-stretch mode disregards the page-mode input so that read data cycles in nonpage-mode
read-modify-write sequences are stretched even though there are no timing constraints that require
a stretch.
d) All other memory subcycles are not stretched, even if the SMJ34020A is running with the CSE bit
set to 1.
The advantage of this implementation of clock-stretch mode is that the SMJ34020A can execute code at
maximum speed, slowing down only during certain parts of memory access sequences.
It is important to remember that a stretched cycle is 25% longer than a normal cycle and that the SMJ34020A
(with the exception of the video logic, which is clocked independently by VCLK) effectively slows down during
such a stretched cycle.
Figure 5 through Figure 8 show examples of stretch-mode memory operations.
ADDR
READ
ADDR
READ
1234123412341234
Stretch Mode Disabled
ADDR
READ
ADDR
READ
Stretch Mode Enabled
123441234123441234
Stretch
Stretch
Figure 5. Two 32-Bit Nonpage-Mode Reads
ADDR
READ
WRITE
123412341234
Stretch Mode Disabled
ADDR
READ
WRITE
Stretch Mode Enabled
12344123441234
Stretch
Stretch
Figure 6. One 32-Bit Page-Mode Read-Modify-Write
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