SMJ34020A_06 Datasheet, PDF (9/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

functional block diagram
HA5 −HA31 27
HBS0 −HBS3 4
HCS
HREAD
HWRITE
HINT
HRDY
HDST
HOE
GI
R0
R1
EMU0
EMU1
EMU2
EMU3
CLKIN
LCLK1
LCLK2
Host
Address
Latch
Host
Interface
PC
ST
Register
File A
Multi-
Processor
Interface
Register
File B
SP
Emulation
Interface
ALU
System
Clocks
Barrel
Shifter
RESET, LINT1,
LINT2
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
Cache
Decode
I/O
Regs
LRU
Buffer/
Page-mode
Register
MUX
Bus
Control
DRAM/
VRAM
Interface
Local
Memory
and
Bus
Timing
Bus
Interface
Microcontrol ROM
Reset and Interrupts
Video
Timing
and
Control
32 ^{LAD0 −LAD31}
13 _{RCA0 −RCA12}
DDIN
DDOUT
RAS
4 CAS0 −CAS3
WE
TR / QE
ALTCH
SF
PGMD
SIZE16
LRDY
BUSFLT
CAMD
VSYNC
HSYNC
CSYNC / HBLNK
CBLNK / VBLNK
VCLK
SCLK
architecture (continued)
register files
Boolean, arithmetic, pixel-processing, byte, and field-move instructions operate on data within the
general-purpose register files. The SMJ34020A contains two register files of fifteen 32-bit registers and a
system stack pointer (SP). The SP is addressed in both register file A and register file B as a sixteenth register.
Transfers between registers and memory are facilitated using a complete set of field move instructions with
selectable field sizes.
The 15 general-purpose registers in register file A are used for high-level language support and
assembly-language programming. The 15 registers in register file B are dedicated to special functions during
PIXBLTS and other pixel operations but can be used as general-purpose registers at other times.
stack pointer (SP)
The stack pointer is a dedicated 32-bit internal register that points to the top of the system stack.
program counter (PC)
The SMJ34020A’s 32-bit program counter register points to the next instruction-stream word to be fetched.
Since instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
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