SMJ34020A_06 Datasheet, PDF (42/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
The VRAM cycle shown in Figure 21 is issued in any of three ways:
D Pixel operation instruction with CST in DPYCTL set
D Horizontal blank reload cycle requested by the video-control logic with VCE in DPYCTL cleared
D Video timeout due to SCOUNT match with the value in MLRNXT and VCE and SSV in DPYCTL cleared
This cycle is indicated by TR / QE and SF low and CAS and WE high at the time RAS goes low. The timing of
the low-to-high transition of TR / QE is dependent upon the timing of SCLK when doing a midline reload cycle.
During the address portion of the cycle, the status on LAD0 −LAD3 indicates either a video-initiated VRAM
memory-to-register transfer (status code = 0100), or a CPU-initiated VRAM memory-to-register transfer
(status code = 0101).
42
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443