SMJ34020A_06 Datasheet, PDF (52/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
The host-access request is synchronized to the SMJ34020A at the beginning of Q4 so that the local memory
cycle can begin in Q1.
In block mode (prefetch after read), the SMJ34020A automatically initiates sequential read accesses as soon
as the host deasserts the current read request. In this example, the host reads a location and must wait for the
first access to complete. When the host removes HREAD (Figure 28), indicating the end of the first read, the
SMJ34020A starts to prefetch the next sequential location. When the host makes the next request, the
SMJ34020A has prefetched the data so that the host reads with no delay. While in block mode, the SMJ34020A
continues to prefetch data for the host read each time the host removes either HREAD or HCS. If the address
present and latched at the falling edge of HCS matches the previously prefetched address, HRDY is asserted
high so that the host can read with no delay.
In read-modify-write mode (prefetch after write), the SMJ34020A initiates the read access as soon as the current
write request is deasserted.
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