SMJ34020A_06 Datasheet, PDF (6/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
DRAM AND VRAM CONTROL (CONTINUED)
WE
O Write enable. The active low WE drives the WE inputs of DRAMs and VRAMs. WE can also be used as the active
low write enable to static memories and other devices connected to the SMJ34020A local interface. During a
local-memory read cycle, WE remains inactive high while CAS is strobed active low. During a local-memory write
cycle, WE is strobed active low before CAS. During VRAM serial-data-register transfer cycles, the state of WE at
the falling edge of RAS controls the direction of the transfer.
HOST INTERFACE
HA5 −HA31
I
Twenty-seven host address input signals. A host can access a long word by placing the address on these lines.
HA5 −HA31 correspond to LAD5 −LAD31 that output the address to the local memory.
HBS0 −HBS3
I
Four host byte selects. HBS0 −HBS3 identify which bytes within the long word are being selected.
HCS
I
Host chip select. A host drives HCS low to latch the current host address present on HA5 −HA31 and the host byte
selects on HBS0 −HBS3. HCS also enables host access cycles to the SMJ34020A I/O registers or local memory.
During the low-to-high transition of RESET, the level on HCS determines whether the SMJ34020A is halted (HCS
is high for host-present mode) or whether it begins executing its reset service routine (HCS is low for self-bootstrap
mode).
HDST
O Host data-latch strobe. The rising edge of HDST latches data from the SMJ34020A local address space to the
external host data latch on host read accesses. HDST can be used in conjunction with HRDY to indicate that data
is valid in the external data latch.
HINT
O Host Interrupt. HINT allows the SMJ34020A to interrupt a host by setting the INTOUT bit in the HSTCTLL I/O
register. HINT can also be used to interrupt the host if a BUSFLT or RETRY occurs due to a host access cycle.
HOE
O Host data latch output enable. HOE enables data from host data latches to the SMJ34020A local address space
on host write cycles. HOE can be used in conjunction with HRDY to indicate data has been written to memory from
the external data latch.
HRDY
O Host ready. HRDY is normally low and goes high to indicate that the SMJ34020A is ready to complete a
host-initiated read or write cycle. If the SMJ34020A is ready to accept the access request, HRDY is driven high
and the host can proceed with the access. A host can use HRDY logically combined with HDST and HOE to
determine when the local bus access cycles have completed.
HREAD
I
Host read strobe. HREAD is driven low during a read request from a host processor. This notifies the SMJ34020A
that the host is requesting access to the I/O registers or to local memory. HREAD should not be asserted at the
same time that HWRITE is asserted.
HWRITE
I
Host write strobe. HWRITE is driven low to indicate a write request by a host processor. This notifies the
SMJ34020A that a write request is pending. The rising edge of HWRITE is used to indicate that the host has latched
data to be written in the external data transceivers. HWRITE should not be asserted at the same time HREAD is
asserted.
SYSTEM CONTROL
CLKIN
I
Clock input. CLKIN generates LCLK1 and LCLK2, to which all processor functions in the SMJ34020A are
synchronous. A separate asynchronous input clock (VCLK) controls the video timing and video registers.
LCLK1, LCLK2
O Local output clocks. LCLK1 and LCLK2 are 90 degrees out of phase with each other. They provide convenient
synchronous control of external circuitry to the internal timing. All signals output from the SMJ34020A (except the
CRT timing signals) are synchronous to LCLK1 and LCLK2.
LINT1, LINT2
I
Local interrupt requests. Interrupts from external devices are transmitted to the SMJ34020A on LINT1 and LINT2.
Each local interrupt signal activates the request for one of two interrupt request levels. An external device generates
an interrupt request by driving the appropriate interrupt request pin to its active-low state. LINT1, LINT2 should
remain low until the SMJ34020A recognizes it. LINT1, LINT2 can be applied asynchronously to the SMJ34020A
as they are synchronized internally before use.
RESET
I
† _{I = input, O = output}
System reset. During normal operation, RESET is driven low to reset the SMJ34020A. When RESET is asserted
low, the SMJ34020A’s internal registers are set to an initial known state and all output and bidirectional pins are
driven either to inactive levels or to the high-impedance state. The SMJ34020A’s behavior following reset depends
on the level of the HCS input just before the low-to-high transition of RESET. If HCS is low, the SMJ34020A begins
executing the instructions pointed to by the reset vector. If HCS is high, the SMJ34020A is halted until a host
processor writes a 0 to the HLT bit in the HSTCTLL register.
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