SMJ34020A_06 Datasheet, PDF (20/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
multiprocessor arbitration (continued)
The GI priority for multiprocessing environments is determined by arbitration logic external to the SMJ34020A.
If GI goes inactive-high, the SMJ34020A releases the bus on the next available cycle boundary. If the cycle in
progress has not successfully completed, the SMJ34020A restarts the cycle upon regaining control of the bus.
Normally, if the SMJ34020A asserts both R0 and R1 low, it should be given the control of the bus by the arbitrator.
host interface
The SMJ34020A host interface allows the local memory to be mapped into the host address space. The
SMJ34020A acts as a DRAM controller for the host. The address for the host access is latched within the
SMJ34020A; however, the data for the access is transferred using external transceivers. The host selects the
address of a 32-bit long word for an access using the 27 host address lines, HA5−HA31. If the host desires byte
addressability, it can select the active bytes for the access by using HBS0 −HBS3. The SMJ34020A always
reads 32 bits from memory; however, on host writes, it uses the host byte selects to enable CAS0 −CAS3 to
memory. The address and byte selects are latched at the falling edge of HCS within the SMJ34020A. The host
indicates a read or write by asserting HREAD or HWRITE (as appropriate) either before or after HCS. (Note
that HREAD and HWRITE must never be asserted at the same time.)
The SMJ34020A responds to a host read request by latching the requested data in the external latches and
providing HRDY to the host, indicating that the read cycle is completing. The rising edge of HDST with HRDY
high indicates data is latched in the external transceivers.
The host indicates that a write to a particular location is required by providing the address and asserting
HWRITE. The host must maintain both HCS and HWRITE asserted until valid data is in the transceivers. (The
rising edge of HOE with HRDY high indicates that the data previously stored in the external transceivers has
been written to memory.) Typically, the rising edge of HWRITE is used to strobe the data into the latches and
signal the SMJ34020A that the write access can start. The SMJ34020A uses its byte-write capability to write
only to the selected bytes.
The SMJ34020A always accesses the required location as latched at the falling edge of HCS; however, in order
to increase the data rate, a look ahead mechanism is implemented. The host increment enable (HINC) and host
prefetch after write enable (HPFW) bits in the host control register (HSTCTLH) must be appropriately set to
make optimum use of this feature. These bits provide four modes of operation as indicated in Table 6.
Table 6. Modes of Operation
HINC
0
0
1
1
HPFW
0
1
0
1
HOST ACCESS MODE
Random/Same
Random/Same
Block
Read-Modify-Write
DESCRIPTION
No increment, no prefetch
No increment, no prefetch
Increment after read or write, prefetch after read
Increment after write, prefetch after write
When the SMJ34020A is programmed for block mode or read-modify-write accesses, the host can still do
random accesses because the SMJ34020A always uses the address provided at the falling edge of HCS;
however, there is a prefetch to the next sequential address. The prefetch occurs after reads in block mode and
after writes in read-modify-write mode. The SMJ34020A compares the address latched by HCS on host reads
to see if it is the same as that of the last prefetched data. If the addresses match, data is not re-accessed but
HRDY is set high to indicate that the data is presently available.
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