SMJ34020A_06 Datasheet, PDF (27/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
LRDY low at the start of the first Q2 after RAS low (Figure 10) indicates that the memory requires the addition
of wait states. LRDY high at the next Q2 indicates the cycle can continue without inserting more wait states.
PGMD high at the start of Q2 where LRDY is sampled high indicates that this memory does not support
page-mode operation.
LCLCK1
Address Subcycle
Wait State
Read Transfer
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK2
GI
LAD (SMJ34020A)
(see Note A)
LAD (Memory)
(see Note A)
CAMD
Address
Data
RCA
Row
Column
ALTCH
RAS
CAS
WE
TR/ QE
SF
DDIN
DDOUT
LRDY
PGMD
(see Note B)
SIZE16
(see Note B)
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (memory): Output to LAD by the memory.
B. Although they are not internally sampled, PGMD and SIZE16 must be held at a valid level at the
start of each Q2 until LRDY is sampled high.
Figure 10. Local-Memory Read-Cycle Timing (Without Page Mode, With One Wait State)
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