SMJ34020A_06 Datasheet, PDF (58/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
Although RESET is not normally required to be synchronous to CLKIN, in order to facilitate synchronization of
multiple SMJ34020As in a system, the rising edge of RESET must meet the setup and hold requirements to
CLKIN so that all GSPs are certain to respond to the RESET on the same quarter cycle (Figure 31). The four
possible conditions for the state of the SMJ34020A at the time RESET goes high are shown below. Quarter cycle
1 is extended accordingly to provide synchronization of the GSPs. All SMJ34020As to be synchronized must
share a common CLKIN and RESET. Within 10 CLKIN cycles after RESET goes high, all GSPs are
synchronized to the same quarter cycle through the extension of Q1 cycles.
It is recommended that SMJ34020A stretch mode not be used in multiprocessor systems.
CLKIN
RESET
Case 1
LCLK1
LCLK2
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q1
Q2
Case 2
LCLK1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q1
Q1
Q2
LCLK2
Case 3
LCLK1
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q1
Q1
Q1
Q2
LCLK2
Case 4
LCLK1
Q4
Q1
Q2
Q3
Q4
Q1
Q1
Q1
Q1
Q1
Q2
LCLK2
NOTE A: No timing dependencies of LCLK1 and LCLK2 relative to CLKIN or RESET are to be implied from this figure.
Figure 31. Synchronization of Multiple SMJ34020As
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