SMJ34020A_06 Datasheet, PDF (46/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
cycle timing examples (continued)
This VRAM cycle (Figure 24) is performed when a pixel-write instruction is executed with the CST bit in DPYCTL
set. This cycle is indicated by TR / QE and WE low and SF and CAS high at the time RAS goes low. This cycle
does not require the use of SOE of the VRAM and does not affect the status of the serial I / O pins. During the
address portion of the cycle, the status on LAD0 −LAD3 indicates that a CPU-initiated VRAM
register-to-memory transfer (status code = 0101) is being performed. Although PGMD and SIZE16 are ignored
on this cycle, they should be held at valid levels as shown.
Q4 Q1 Q2 Q3 Q4† Q1 Q2 Q3 Q4 Q1
GI
LAD
Address
CAMD
RCA
Row
Tap Point
ALTCH
RAS
CAS
WE
TR / QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
† _{See clock stretch, page 21.}
Figure 24. Serial-Data-Register-to-Memory Cycle Timing (VRAM-Alternate-Write Transfer)
46
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443