SMJ34020A_06 Datasheet, PDF (77/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
host-interface-cycle timing (block-read cycle) (see Notes 5 and 9 and Figure 45)
34020A-32
34020A-40
NO.
UNIT
MIN
MAX
MIN
MAX
26 tw(RDH)
Pulse duration, HREAD high
28
30 tw(RDL)
Pulse duration, HREAD low
18
37
tsu(RDH-CK2L)
Setup time, HREAD high to LCLK2 no longer high,
prefetch read mode
30†
25
ns
15
ns
25†
ns
39 td(CK1H-RYH) Delay time, LCLK1 no longer low to HRDY high
tQ + 20
tQ + 18 ns
40 td(RDH-RYL) Delay time, HREAD or HCS high to HRDY low
20
18 ns
41 td(CK2L-STL) Delay time, LCLK2 no longer high to HDST low
tQ + 15+s
tQ + 13.5 + s ns
42 td(CK1L-STH) Delay time, LCLK1 no longer high to HDST high
tQ + 15
tQ + 13.5 ns
43 tsu(STL-RYH) Setup time, HDST low to HRDY no longer low
tQ−15
tQ −13.5
ns
44 td(RYH-STH) Delay time, HRDY no longer low to HDST high
2tQ + 15
2tQ + 13.5 ns
45
td(RDL-RYH)
Delay time, HREAD or HCS low to HRDY high after
prefetch
25
20 ns
50 th(STH-CTV)
Hold time, CAS, TR / QE, DDIN valid after HDST high − 2
−2
ns
† _{Setup time to ensure recognition of input on this clock edge. When the SMJ34020A is set for block reads, the deassertion of HREAD is used}
to request a local memory cycle at the next sequential address location.
NOTES: 5. s = tQ if using the clock stretch;
s = 0 otherwise
9. Although HCS, HREAD, and HWRITE can be totally asynchronous to the SMJ34020A, cycle responses to the signals are
determined by local memory cycles.
LCLK1
Q4 Q1 Q2 Q3 Q4‡ Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
LCLK2
HCS
HREAD
HRDY
HDST
CAS
37
26
30
40
45
39
43
41
37
26
40
42
44
50
TR / QE
DDIN
‡ _{See clock stretch, page 21.}
Figure 45. Host-Interface-Cycle Timing (Block-Read Cycle)
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