SMJ34020A_06 Datasheet, PDF (2/97 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
description
The SMJ34020A graphics system processor (GSP) is the second generation of an advanced high-performance
CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability
to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics
operations, the SMJ34020A provides user-programmable control of the CRT interface as well as the memory
interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address
space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics
addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.
architecture
The SMJ34020A is a CMOS 32-bit processor with hardware support for graphics operations such as pixel block
transfers (PIXBLTS) during raster operations and curve-drawing algorithms. Also included is a complete set of
general-purpose instructions with addressing modes tuned to support high-level languages. In addition to its
ability to address a large external memory range, the SMJ34020A contains 30 general-purpose 32-bit registers,
a hardware stack pointer, and a 512-byte instruction cache. On-chip functions include 64 programmable I/O
registers that control CRT timing, input / output control, and parameters required by some instructions. The
SMJ34020A directly interfaces to DRAMs and VRAMs and generates raster control signals. The SMJ34020A
can be configured to operate as a standalone processor, or it can be used as a graphics engine with a host
system. The host interface provides a generalized communication port for any standard host processor. The
SMJ34020A also accommodates a multiprocessing or direct memory access (DMA) environment through the
request / grant interface protocols. Virtual memory systems are supported through bus-fault detection and
instruction continuation.
The SMJ34020A provides single-cycle execution of general-purpose instructions and most common integer
arithmetic and Boolean operations from its instruction cache. Additionally, the SMJ34020A incorporates a
hardware barrel shifter that provides a single-state bidirectional shift-and-rotate function for 1 to 32 bits.
The local-memory controller is designed to optimize memory access operations. It also supports pipeline
memory write operations of variable-sized fields and allows memory access and instruction execution in
parallel.
The SMJ34020A graphics-processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems at a variety of pixel sizes. The hardware incorporates two-operand and
three-operand raster operations with Boolean and arithmetic operations, XY addressing, window clipping,
window-checking operations, 1 to n bits-per-pixel transforms, transparency, and plane masking. The
architecture further supports operations on single pixel transfer (PIXT) instructions or on two-dimensional
arrays of arbitrary size (PIXBLTS).
The SMJ34020A’s flexible graphics-processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include clipping to arbitrary window size, custom incremental-curve
drawing, two-operand raster operations, and masked two-operand raster operations.
The SMJ34020A provides for extensions to the basic architecture through the coprocessor interface. Special
instructions and cycle timings are included to enhance data flow to coprocessors without requiring the
coprocessor to decode the instruction stream, generate system addresses, or move data for the coprocessor
through the SMJ34020A.
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