HD64F3687HV Datasheet, PDF (99/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 4 Address Break
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 22.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
ROM space
RAM space
I/O register with 8-bit data
bus width
I/O register with 16-bit data
bus width
Word Access
Even Address Odd Address
Upper 8 bits Lower 8 bits
Upper 8 bits Lower 8 bits
Upper 8 bits Upper 8 bits
Upper 8 bits Lower 8 bits
Byte Access
Even Address Odd Address
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits


4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Initial
Bit
Bit Name Value
7
ABIF
0
6
ABIE
0
5 to 0 
All 1
R/W
R/W
R/W

Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
Rev.5.00 Nov. 02, 2005 Page 65 of 500
REJ09B0027-0500