HD64F3687HV Datasheet, PDF (233/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.4 Operation
13.4.1 Counter Operation
When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example. Figure 13.7 shows an example of the counter operation setting procedure.
Operation selection
Select counter clock [1]
Periodic counter
Select counter clearing source [2]
Select output compare register [3]
Set period
[4]
Start count operation
[5]
Free-running counter
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. When an external
clock is selected, select
the external clock edge
with bits CKEG1
and CKEG0 in TCR.
[2] For periodic counter
operation, select the
TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
[3] Designate the general
register selected in [2]
as an output compare
register by means of
TIOR.
[4] Set the periodic counter
cycle in the general
register selected
in [2].
[5] Set the STR bit in TSTR
to 1 to start the counter
operation.
Figure 13.7 Example of Counter Operation Setting Procedure
1. Free-running count operation and periodic count operation
Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as free-
running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter
starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag
in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point,
timer Z requests an interrupt. After overflow, TCNT starts an increment operation again from
H'0000.
Rev.5.00 Nov. 02, 2005 Page 199 of 500
REJ09B0027-0500