HD64F3687HV Datasheet, PDF (408/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 22 List of Registers
22.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register
—
Timer control register_0
Timer I/O control register A_0
Timer I/O control register C_0
Timer status register_0
Timer interrupt enable register_0
PWM mode output level control
register_0
Timer counter_0
General register A_0
General register B_0
General register C_0
General register D_0
Timer control register_1
Timer I/O control register A_1
Timer I/O control register C_1
Timer status register_1
Timer interrupt enable register_1
PWM mode output level control
register_1
Timer counter_1
General register A_1
General register B_1
Abbre-
Module
viation Bit No Address Name
—
—
H'F000 —
to
H'F6FF
TCR_0 8
H'F700 Timer Z
TIORA_0 8
H'F701 Timer Z
TIORC_0 8
H'F702 Timer Z
TSR_0 8
H'F703 Timer Z
TIER_0 8
H'F704 Timer Z
POCR_0 8
H'F705 Timer Z
TCNT_0 16
GRA_0 16
GRB_0 16
GRC_0 16
GRD_0 16
TCR_1 8
TIORA_1 8
TIORC_1 8
TSR_1 8
TIER_1 8
POCR_1 8
H'F706
H'F708
H'F70A
H'F70C
H'F70E
H'F710
H'F711
H'F712
H'F713
H'F714
H'F715
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
TCNT_1 16
GRA_1 16
GRB_1 16
H'F716
H'F718
H'F71A
Timer Z
Timer Z
Timer Z
Data
Bus
Width
—
Access
State
—
8
2
8
2
8
2
8
2
8
2
8
2
16
2
16
2
16
2
16
2
16
2
8
2
8
2
8
2
8
2
8
2
8
2
16
2
16
2
16
2
Rev.5.00 Nov. 02, 2005 Page 374 of 500
REJ09B0027-0500