HD64F3687HV Datasheet, PDF (70/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 2 CPU
Specified
by @aa:8
Dummy
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No Addressing Mode and Instruction Format
1 Register direct(Rn)
op rm rn
2 Register indirect(@ERn)
op
r
3 Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
op
r
disp
Effective Address Calculation
31
0
General register contents
31
0
General register contents
31
Sign extension
0
disp
Effective Address (EA)
Operand is general register contents.
23
0
23
0
4 Register indirect with post-increment or
pre-decrement
31
0
23
0
•Register indirect with post-increment @ERn+
General register contents
op
r
1, 2, or 4
•Register indirect with pre-decrement @-ERn
31
0
General register contents
23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Rev.5.00 Nov. 02, 2005 Page 36 of 500
REJ09B0027-0500