HD64F3687HV Datasheet, PDF (226/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.3.10 Timer I/O Control Register (TIORA and TIORC)
The TIOR registers control the general registers (GR). Timer Z has four TIOR registers
(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including
complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.
TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORA
also selects the function of FTIOA or FTIOB pin.
Initial
Bit
Bit Name value R/W Description
7

1

Reserved
This bit is always read as 1.
6
IOB2
0
R/W I/O Control B2 to B0
5
IOB1
0
R/W GRB is an output compare register:
4
IOB0
0
R/W 000: Disables pin output by compare match
001: 0 output by GRB compare match
010: 1 output by GRB compare match
011: Toggle output by GRB compare match
GRB is an input capture register:
100: Input capture to GRB at the rising edge
101: Input capture to GRB at the falling edge
11X: Input capture to GRB at both rising and falling edges
3

1

Reserved
This bit is always read as 1.
2
IOA2
0
R/W I/O Control A2 to A0
1
IOA1
0
R/W GRA is an output compare register:
0
IOA0
0
R/W 000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
Legend: X: Don't care
Rev.5.00 Nov. 02, 2005 Page 192 of 500
REJ09B0027-0500