HD64F3687HV Datasheet, PDF (225/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.3.9 Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Initial
Bit
Bit Name value R/W Description
7
CCLR2 0
R/W Counter Clear 2 to 0
6
CCLR1 0
R/W 000: Disables TCNT clearing
5
CCLR0 0
R/W 001: Clears TCNT by GRA compare match/input
capture*¹
010: Clears TCNT by GRB compare match/input
capture*¹
011: Synchronization clear; Clears TCNT in synchronous
with counter clearing of the other channel’s timer*²
100: Disables TCNT clearing
101: Clears TCNT by GRC compare match/input
capture*¹
110: Clears TCNT by GRD compare match/input
capture*¹
111: Synchronization clear; Clears TCNT in synchronous
with counter clearing of the other channel’s timer*²
4
CKEG1 0
R/W Clock Edge 1 and 0
3
CKEG0 0
R/W 00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2
TPSC2 0
R/W Time Prescaler 2 to 0
1
TPSC1 0
R/W 000: Internal clock: count by φ
0
TPSC0 0
R/W 001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
When GR functions as input capture, TCNT is cleared by input capture.
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Rev.5.00 Nov. 02, 2005 Page 191 of 500
REJ09B0027-0500