HD64F3687HV Datasheet, PDF (28/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 17.2 External Circuit Connections of I/O Pins ................................................................ 305
Figure 17.3 I²C Bus Formats ...................................................................................................... 318
Figure 17.4 I²C Bus Timing........................................................................................................ 318
Figure 17.5 Master Transmit Mode Operation Timing (1)......................................................... 320
Figure 17.6 Master Transmit Mode Operation Timing (2)......................................................... 320
Figure 17.7 Master Receive Mode Operation Timing (1) .......................................................... 322
Figure 17.8 Master Receive Mode Operation Timing (2) .......................................................... 323
Figure 17.9 Slave Transmit Mode Operation Timing (1) ........................................................... 324
Figure 17.10 Slave Transmit Mode Operation Timing (2) ......................................................... 325
Figure 17.11 Slave Receive Mode Operation Timing (1)........................................................... 326
Figure 17.12 Slave Receive Mode Operation Timing (2)........................................................... 326
Figure 17.13 Clocked Synchronous Serial Transfer Format....................................................... 327
Figure 17.14 Transmit Mode Operation Timing......................................................................... 328
Figure 17.15 Receive Mode Operation Timing .......................................................................... 329
Figure 17.16 Block Diagram of Noise Conceler ........................................................................ 329
Figure 17.17 Sample Flowchart for Master Transmit Mode ...................................................... 330
Figure 17.18 Sample Flowchart for Master Receive Mode ........................................................ 331
Figure 17.19 Sample Flowchart for Slave Transmit Mode......................................................... 332
Figure 17.20 Sample Flowchart for Slave Receive Mode .......................................................... 333
Figure 17.21 The Timing of the Bit Synchronous Circuit .......................................................... 335
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 338
Figure 18.2 A/D Conversion Timing.......................................................................................... 344
Figure 18.3 External Trigger Input Timing ................................................................................ 345
Figure 18.4 A/D Conversion Accuracy Definitions (1).............................................................. 347
Figure 18.5 A/D Conversion Accuracy Definitions (2).............................................................. 347
Figure 18.6 Analog Input Circuit Example ................................................................................ 348
Section 19 EEPROM
Figure 19.1 Block Diagram of EEPROM................................................................................... 350
Figure 19.2 EEPROM Bus Format and Bus Timing .................................................................. 352
Figure 19.3 Byte Write Operation .............................................................................................. 355
Figure 19.4 Page Write Operation .............................................................................................. 356
Figure 19.5 Current Address Read Operation............................................................................. 357
Figure 19.6 Random Address Read Operation ........................................................................... 358
Figure 19.7 Sequential Read Operation (when current address read is used)............................. 358
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 362
Figure 20.2 Operational Timing of Power-On Reset Circuit...................................................... 366
Figure 20.3 Operational Timing of LVDR Circuit ..................................................................... 367
Rev.5.00 Nov. 02, 2005 Page xxvi of xxxii