HD64F3687HV Datasheet, PDF (217/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.3.2 Timer Mode Register (TMDR)
TMDR selects buffer operation settings and synchronized operation.
Initial
Bit
Bit Name Value
7
BFD1
0
6
BFC1
0
5
BFD0
0
4
BFC0
0
3 to 1 
All 1
0
SYNC
0
R/W
R/W
R/W
R/W
R/W

R/W
Description
Buffer Operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
Buffer Operation C1
0: GRC_1 operates normally
1: GRA_1 and GRD_1 are used together for buffer
operation
Buffer Operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
Buffer Operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
Reserved
These bits are always read as 1, and cannot be modified.
Timer Synchronization
0: TCNT_1 and TCNT_0 operate as a different timer
1: TCNT_1 and TCNT_0 are synchronized
TCNT_1 and TCNT_0 can be pre-set or cleared
synchronously
Rev.5.00 Nov. 02, 2005 Page 183 of 500
REJ09B0027-0500