HD64F3687HV Datasheet, PDF (526/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

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Page Revision (See Manual for Details)
Section 6 Power-Down 76
Modes
6.1.1 System Control
Register 1 (SYSCR1)
Bit
Bit Name Description
3 NESEL Noise Elimination Sampling Frequency
Select
The subclock pulse generator generates the
watch clock signal (φ_W) and the system clock
pulse generator generates the oscillator
clock (φ_OSC). This bit selects the sampling
frequency of the oscillator clock when the
watch clock signal (φ_W) is sampled. When
φ_OSC = 4 to 20 MHz, clear NESEL to 0.
Section 8 RAM
107 ^{Note: * When the E7 or E8 is used, area H'F780 to H'FB7F}
must not be accessed.
Section 13 Timer Z
208
Figure 13.17 Example of
Input Capture Operation
TCNT value
H'0180
H'0160
Counter cleared by FTIOB input (falling edge)
13.4.4 Synchronous
Operation
13.4.5 PWM Mode
211 Figure 13.20 shows an example of synchronous operation. In
this example, synchronous operation has been selected,
FTIOB0 and FTIOB1 have been designated for PWM mode,
GRA_0 compare match has been set as the channel 0 counter
clearing source, and synchronous clearing has been set for the
channel 1 counter clearing source. In addition, the same input
clock has been set as the counter input clock for channel 0 and
channel 1. Two-phase PWM waveforms are output from pins
FTIOB0 and FTIOB1.
213 Figure 13.22 shows an example of operation in PWM mode.
The output signals go to 1 and TCNT is reset at compare
match A, and the output signals go to 0 at compare match B,
C, and D (TOB, TOC, and TOD = 1, POLB, POLC, and POLD
= 0).
214 Figures 13.24 (when TOB, TOC, and TOD = 1, POLB, POLC,
and POLD = 0) and 13.25 (when TOB, TOC, and TOD = 0,
POLB, POLC, and POLD = 1) show examples of the output of
PWM waveforms with duty cycles of 0% and 100% in PWM
mode.
Rev.5.00 Nov. 02, 2005 Page 492 of 500
REJ09B0027-0500