HD64F3687HV Datasheet, PDF (221/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.3.5 Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for
inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output
for timer Z.
Initial
Bit
Bit Name Value R/W Description
7
ED1
1
R/W Master Enable D1
0: FTIOD1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOD1 pin is operated
as an I/O port).
6
EC1
1
R/W Master Enable C1
0: FTIOC1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOC1 pin is operated
as an I/O port).
5
EB1
1
R/W Master Enable B1
0: FTIOB1 pin output is enabled according to the TPMR,
TFCR, and TIORA_1 settings
1: FTIOB1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOB1 pin is operated
as an I/O port).
4
EA1
1
R/W Master Enable A1
0: FTIOA1 pin output is enabled according to the TPMR,
TFCR, and TIORA_1 settings
1: FTIOA1 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_1 settings (FTIOA1 pin is operated
as an I/O port).
3
ED0
1
R/W Master Enable D0
0: FTIOD0 pin output is enabled according to the TPMR,
TFCR, and TIORC_0 settings
1: FTIOD0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOD0 pin is operated
as an I/O port).
Rev.5.00 Nov. 02, 2005 Page 187 of 500
REJ09B0027-0500