HD64F3687HV Datasheet, PDF (222/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Initial
Bit
Bit Name Value R/W Description
2
EC0
1
R/W Master Enable C0
0: FTIOC0 pin output is enabled according to the TPMR,
TFCR, and TIORC_0 settings
1: FTIOC0 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_0 settings (FTIOC0 pin is operated
as an I/O port).
1
EB0
1
R/W Master Enable B0
0: FTIOB0 pin output is enabled according to the TPMR,
TFCR, and TIORA_0 settings
1: FTIOB0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOB0 pin is operated
as an I/O port).
0
EA0
1
R/W Master Enable A0
0: FTIOA0 pin output is enabled according to the TPMR,
TFCR, and TIORA_0 settings
1: FTIOA0 pin output is disabled regardless of the TPMR,
TFCR, and TIORA_0 settings (FTIOA0 pin is operated
as an I/O port).
13.3.6 Timer Output Control Register (TOCR)
TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
Initial
Bit
Bit Name Value R/W Description
7
TOD1
0
R/W Output Level Select D1
0: 0 output at the FTIOD1 pin*
1: 1 output at the FTIOD1 pin*
6
TOC1
0
R/W Output Level Select C1
0: 0 output at the FTIOC1 pin*
1: 1 output at the FTIOC1 pin*
5
TOB1
0
R/W Output Level Select B1
0: 0 output at the FTIOB1 pin*
1: 1 output at the FTIOB1 pin*
Rev.5.00 Nov. 02, 2005 Page 188 of 500
REJ09B0027-0500