HD64F3687HV Datasheet, PDF (229/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Initial
Bit
Bit Name value R/W Description
2
IMFC
0
R/W Input Capture/Compare Match Flag C
[Setting conditions]
• When TCNT = GRC and GRC is functioning as output
compare register
• When TCNT value is transferred to GRC by input
capture signal and GRC is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFC after reading IMFC = 1
1
IMFB
0
R/W Input Capture/Compare Match Flag B
[Setting conditions]
• When TCNT = GRB and GRB is functioning as output
compare register
• When TCNT value is transferred to GRB by input
capture signal and GRB is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFB after reading IMFB = 1
0
IMFA
0
R/W Input Capture/Compare Match Flag A
[Setting conditions]
• When TCNT = GRA and GRA is functioning as output
compare register
• When TCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFA after reading IMFA = 1
Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
Rev.5.00 Nov. 02, 2005 Page 195 of 500
REJ09B0027-0500