HD64F3687HV Datasheet, PDF (376/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 18 A/D Converter
Initial
Bit Bit Name Value R/W Description
2
CH2
0
R/W Channel Select 2 to 0
1
CH1
0
R/W Select analog input channels.
0
CH0
0
R/W When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 and AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
100: AN4
100: AN4
101: AN5
101: AN4 and AN5
110: AN6
110: AN4 to AN6
111: AN7
111: AN4 to AN7
18.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Initial
Bit Bit Name Value R/W
7
TRGE
0
R/W
6 to 1 —
0
—
All 1 —
0
R/W
Description
Trigger Enable
A/D conversion is started at the falling edge and the rising
edge of the external trigger signal (ADTRG) when this bit
is set to 1.
The selection between the falling edge and rising edge of
the external trigger pin (ADTRG) conforms to the WPEG5
bit in the interrupt edge select register 2 (IEGR2)
Reserved
These bits are always read as 1.
Reserved
Do not set this bit to 1, though the bit is readable/writable.
Rev.5.00 Nov. 02, 2005 Page 342 of 500
REJ09B0027-0500