HD64F3687HV Datasheet, PDF (281/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
6. Contention between Count Clearing and Increment Operations by Input Capture: If an input
capture and increment signals are simultaneously generated, count clearing by the input
capture operation has priority without an increment operation. The TCNT contents before
clearing counter are transferred to GR. Figure 13.57 shows the timing in this case.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
N
H'0000
GR
N
Clearing has priority.
Figure 13.57 Contention between Count Clearing and Increment Operations
by Input Capture
Rev.5.00 Nov. 02, 2005 Page 247 of 500
REJ09B0027-0500