HD64F3687HV Datasheet, PDF (223/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Initial
Bit
Bit Name Value R/W Description
4
TOA1
0
R/W Output Level Select A1
0: 0 output at the FTIOA1 pin*
1: 1 output at the FTIOA1 pin*
3
TOD0
0
R/W Output Level Select D0
0: 0 output at the FTIOD0 pin*
1: 1 output at the FTIOD0 pin*
2
TOC0
0
R/W Output Level Select C0
0: 0 output at the FTIOC0 pin*
1: 1 output at the FTIOC0 pin*
1
TOB0
0
R/W Output Level Select B0
0: 0 output at the FTIOB0 pin*
1: 1 output at the FTIOB0 pin*
0
TOA0
0
R/W Output Level Select A0
0: 0 output at the FTIOA0 pin*
1: 1 output at the FTIOA0 pin*
Note: * The change of the setting is immediately reflected in the output value.
13.3.7 Timer Counter (TCNT)
The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT
counters are 16-bit readable/writable registers that increment/decrement according to input clocks.
Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1
increment/decrement in complementary PWM mode, while they only increment in other modes.
The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB,
GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When
the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When
TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8-
bit units; they must always be accessed as a 16-bit unit.
Rev.5.00 Nov. 02, 2005 Page 189 of 500
REJ09B0027-0500