HD64F3687HV Datasheet, PDF (60/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 2 CPU
Table 2.4 Logic Operations Instructions
Instruction Size* Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev.5.00 Nov. 02, 2005 Page 26 of 500
REJ09B0027-0500