HD64F3687HV Datasheet, PDF (282/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T₂ state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 13.58 shows the timing in this case.
φ
Address bus
WGR
(internal write signal)
Input capture
signal
TCNT
GR write cycle
T1
T2
GR address
N
GR
M
GR write data
Figure 13.58 Contention between GR Write and Input Capture
Rev.5.00 Nov. 02, 2005 Page 248 of 500
REJ09B0027-0500