HD64F3687HV Datasheet, PDF (338/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 17 I²C Bus Interface 2 (IIC2)
SCL
SDA
Output
control
Noise canceler
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
Bus state
decision circuit
Arbitration
decision circuit
ICIER
ICSR
[Legend]
ICCR1 : I²C bus control register 1
ICCR2 : I²C bus control register 2
ICMR : I²C bus mode register
ICSR : I²C bus status register
ICIER : I²C bus interrupt enable register
ICDRT : I²C bus transmit data register
ICDRR : I²C bus receive data register
ICDRS : I²C bus shift register
SAR : Slave address register
Interrupt
generator
Figure 17.1 Block Diagram of I²C Bus Interface 2
Interrupt request
Rev.5.00 Nov. 02, 2005 Page 304 of 500
REJ09B0027-0500