HD64F3687HV Datasheet, PDF (265/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Input capture
signal
Buffer register
General
register
TCNT
Figure 13.36 Input Capture Buffer Operation
3. Complementary PWM Mode
When the counter switches from counting up to counting down or vice versa, the value of the
buffer register is transferred to the general register. Here, the value of the buffer register is
transferred to the general register in the following timing:
A. When TCNT_0 and GRA_0 are compared and their contents match
B. When TCNT_1 underflows
4. Reset Synchronous PWM Mode
The value of the buffer register is transferred from compare match A0 to the general register.
5. Example of Buffer Operation Setting Procedure
Figure 13.37 shows an example of the buffer operation setting procedure.
Buffer operation
Select GR function
Set buffer operation
[1] Designate GR as an input capture register
or output compare register by means of
TIOR.
[2] Designate GR for buffer operation with bits
[1]
BFD1, BFC1, BFD0, or BFC0 in TMDR.
[3] Set the STR bit in TSTR to 1 to start the
count operation of TCNT.
[2]
Start count operation
[3]
<Buffer operation>
Figure 13.37 Example of Buffer Operation Setting Procedure
Rev.5.00 Nov. 02, 2005 Page 231 of 500
REJ09B0027-0500