HD64F3687HV Datasheet, PDF (274/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.5 Interrupts
There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
13.5.1 Status Flag Set Timing
1. IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated
when the GR matches with the TCNT. The compare match signal is generated at the last state
of matching (timing to update the counter value when the GR and TCNT match). Therefore,
when the TCNT and GR matches, the compare match signal will not be generated until the
TCNT input clock is generated. Figure 13.48 shows the timing to set the IMF flag.
φ
TCNT input clock
TCNT
N
N+1
GR
N
Compare match
signal
IMF
ITMZ
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs
Rev.5.00 Nov. 02, 2005 Page 240 of 500
REJ09B0027-0500